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three phase multifunction energy metering ic with spi interface spec - 0447 (rev. 7) 1 / 18 2 9 - 09 - 2017 sa9904b features ? bidirectional active and reactive power/energy measurement ? rms voltage and frequency measurement ? individual phase information ? spi communication bus ? meets the iec 61036 specification requirements for class 1 ac watt hour meters ? meets the iec 61268 specification requirements for class 2 ac var hour meters ? protected against esd ? total power consumption rating below 60mw ? uses current transformers for current sensing ? operate s over a wide temperature range ? precision on - chip voltage reference ? measures ac inputs only description the sa9904b is a three phase bidirectional energy/power metering integrated circuit that has been designed to measure active and reactive energy, rms mains voltage and mains frequency. the sa9904b has an integrated spi serial interface for communication with a microcontroller. measured values for active and reactive energy, the mains voltage and frequency for each phase are accessible through the spi interface from 24 bit registers. the sa9904b active and reactive en ergy registers are capable of holding at least 52 seconds of accumulated energy at full load. a mains voltage zero crossover is available on the f50 output. the sa9904b includes all the required functions for three phase power and energy measurement suc h as oversampling a/d converters for the voltage and current sense inputs, power calculation and energy integration. this innovative universal three phase power/energy metering integrated circuit is ideally suited for energy calculations in applications su ch as electricity dispensing systems, residential metering and factory energy metering and control. the sa 9904b integrated circuit is available in a 2 0 pin small outline (soic2 0 ) rohs compliant package. figure 1 : block diagram vref vss osc1 osc2 oscillator and timing voltage reference and current biasing agnd vdd power on reset signal processing voltage channel adc current channel adc ivp1 - 3 iin1 - 3 iip1 - 3 digital output digital output instantaneous power f50 di do spi interface cs sck active power register 90 degree phase shift instantaneous power reactive power register vrms calculation vrms register frequency register repeated 3 times, once for each device channel
spec - 0447 (rev. 7) 2 / 18 2 9 - 09 - 2017 sa9904b electrical characteristics ( v dd - v ss = 5v 10 %, over the temperature range - 40 c to +85c, unless otherwise specified. refer to figure 2 test circuit for electrical characteristics.) parameter symbol min typ max unit condition general supply voltage: positive v dd 2. 25 2.5 2. 75 v with respect to agnd supply voltage: negative v ss - 2. 75 - 2.5 - 2. 25 v with respect to agnd supply current: positive i dd 9.5 11 ma supply current: negative i ss - 9.5 - 11 ma analog inputs current sensor inputs (differential) input current range ir iip1 , ir iip2 , ir iip3 , ir iin1 , ir iin2 , ir iin3 - 25 25 a peak value offset voltage vo iip1 , vo iip2 , vo iip3 , vo iin1 , vo iin2 , vo iin3 - 4 4 mv with r = 4.7k ? voltage sensor inputs (asymmetrical) input current range ir ivp1 , ir ivp2 , ir ivp3 - 25 25 a ivp1 , vo ivp2 , vo ivp3 - 4 4 mv with r = 4.7k ? digital inputs sck, cs, di input high voltage input low voltage v ih v il v dd - 1 v ss +1 v v sck maximum clock frequency minimum clock low time minimum clock high time f sck t lo t hi 0.6 0.6 800 khz s s digital outputs f50, do output high voltage output low voltage v oh v ol v dd - 1 v ss +1 v v i source = 5ma i sink = 5ma during manufacturing, testing and shipment we take great care to protect our products against potential external environmental damage such as electrostatic discharge (esd). although our products have esd protection circuitry, permanent damage may occur on products subjected to high - energy electrostatic discharges accumulated on the human body and/or test equipment th at can discharge without detection. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality during product handling. attention: electrostatic sensitive device. requires special handling.
spec - 0447 (rev. 7) 3 / 18 2 9 - 09 - 2017 sa9904b electrical characteristics (continued) ( v dd - v ss = 5v 10 %, over the temperature range - 40 c to +85c, unless otherwise specified. refer to figure 2 test circuit for electrical characteristics.) parameter symbol min typ max unit condition on - chip voltage reference reference voltage v r 1.1 5 1.20 1. 25 v reference current - i r 24.4 25.5 26.6 a ? ss temperature coefficient tc r 10 70 ppm/oc oscillator recommended crystal f osc 3.5795 mhz tv colour burst crystal absolute maximum ratings* parameter symbol min max unit supply voltage v dd - v ss 6 v current on any pin i pin - 150 150 ma storage temperature t stg - 60 +125 oc specified operating temperature range t o - 40 +85 oc limit range of operating temperature t limit - 40 +85 oc *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other condition above those indicated in the operational sections of this specification, is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. figure 2 : test circuit for electrical characteristics sa9904b r6 r4 r1 0.2a to 100a 50hz ac phase 1 220v 50hz ac phase 1 iin1 iip1 vref vss vss cs sck vdd vdd r10 + - + - gnd gnd vdd vss gnd r1: 1.2 ? r2: 1.2 ? r3: 1.5k ? r4: 1.5k ? r5: 1.5k ? r6: 1.5k ? r7: 250k ? r8: 1k ? r9: 100k ? r10: 47k ? ct1 : tz76v (2500:1) p1: 1k ? c1: 22nf c2: 22nf c3: 5.6nf c4: 220nf c5: 220nf c6: 1 f x1: 3.5795mhz ct1 do 2.5v dc 2.5v dc vdd vss c4 c5 c6 phase angle between voltage and current 0 to 360 gnd ivp1 n n three phase source di osc2 osc1 agnd r3 r5 c2 c1 r2 iin2 iip2 same as iip1 / iin1 input network 0.2a to 100a 50hz ac phase 2 iin3 iip3 same as iip1 / iin1 input network 0.2a to 100a 50hz ac phase 3 r9 c3 gnd gnd r7 r8 p1 220v 50hz ac phase 2 n 220v 50hz ac phase 3 n same as ivp1 input network ivp2 same as ivp1 input network ivp3 x1 f50 spi interface to controller
spec - 0447 (rev. 7) 4 / 18 2 9 - 09 - 2017 sa9904b p in description designation pin no. description agnd 16 analog ground. this is the reference pin for the current and voltage signal sensing networks. the supply voltage to this pin should be mid - way between v dd and v ss . v dd 6 positive supply voltage. the voltage to this pin should be +2.5v 10 % with respect to agnd. v ss 1 4 negative supply voltage. the voltage to this pin should be - 2.5v 10 % with respect to agnd. ivp1, ivp2, ivp3 17, 20 , 3 analog inputs for voltages. the nominal current into the voltage sense inputs ivp should be set at 1 4 a rms . the voltage sense inputs saturate at an input current of 25a peak. iip1, iin1, iip2, iin2, iip3, iin3 18 , 19 , 1, 2, 4, 5 analog inputs for currents. the maximum current into the current sense inputs iip/iin should be set at 16a rms . the current sense inputs saturate at an input current of 25a peak. vref 1 5 this pin provides the connection for the reference current setting resistor. a 47k ? resistor connected to v ss sets the optimum operating conditions. osc1, osc2 10, 11 connection for crystal sck 8 spi serial clock input. this pin is used to strobe data in and out of the sa9904b cs 13 spi chip select input. this input pin enables the spi interface. it is active high. di 12 spi data in input. input data is accepted on this pin at the rising clock edge on sck when cs is active. do 9 spi data out output. output data is strobed out on this pin at the rising clock edge on sck when cs is active. do is not driven when cs is inactive. f50 7 voltage zero crossover. the f50 output generates a pulse on every rising edge of the mains voltage of an active channel. figure 3 : pin connections ordering information part number package sa 9904b sa r soic2 0 (rohs compliant) 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 iip2 iin2 ivp3 iip3 iin3 vdd f50 sck ivp2 iin1 ivp1 vref vss cs 9 10 12 11 do osc1 di osc2 iip1 agnd
spec - 0447 (rev. 7) 5 / 18 2 9 - 09 - 2017 sa9904b terminology positive energy positive energy is defined when the phase difference between the input signals iip and ivp is less than 90 degrees ( - 90..90 degrees). negative energy negative energy is defined when the phase difference between the input signals iip and ivp is greater than 90 degrees (90..270 degrees). percentage error* percentage error is given by the following formula: % ????? = ?????? ?????????? ? ???? ????? ? ???? ?????? 100 note: since the true value cannot be determined, it is approximated by a value with a stated uncertainty that can be traced to standards agreed upon between manufacturer and user or to national standards. rated operating condit ions* set of specified measuring ranges for performance characteristics and specified operating ranges for influence quantities, within which the variations or operating errors of a meter are specified and determined. specified measuring range* set of val ues of a measured quantity for which the error of a meter is intended to lie within specified limits. specified operating range* a range of values of a single influence quantity, which forms a part of the rated operating conditions. limit range of oper ation* extreme conditions which an operating meter can withstand without damage and without degradation of its metrological characteristics when it is subsequently operated under its rated operating conditions. maximum rated mains current (i max ) maximum rated mains current is the specified maximum current flowing through the energy meter at rated operating conditions. constant* value expressing the relation between the active energy registered by the meter and the corresponding value of the test output. if this value is a number of pulses, the constant should be either pulses per kilowatt - hour (imp/kwh) or watt - hours per pulse (wh/imp). nominal mains voltage (v nom ) nominal mains voltage (v nom ) is the voltage specified for the energy meter at rated operat ing conditions. maximum channel energy (e max ) the maximum channel energy is defined as the energy registered on the active register on one channel of the sa 9904b when 14a rms and 16a rms input current with zero phase shift are applied to the voltage and c urrent inputs respectively . both the voltage and current inputs saturate at an input current magnitude of 25a, or at 17.68a rms when using sine waves. the maximum input current on any channel is therefore defined to be 16a rms , which leaves about 10% head room to the saturation point. an additional headroom of 15% is reserved on the voltage channel s to account for mains voltage fluctuations. the nominal output frequency of 320000 counts per second per channel is achieved under such conditions. * iec 62052 - 11, 2003. electricity metering equipment (ac) C general requirements, test and test conditions C part 11: metering equipment
spec - 0447 (rev. 7) 6 / 18 2 9 - 09 - 2017 sa9904b performance graphs figure 4 : test circuit for performance graphs graph 1: active energy, freq = 50hz, vmains = v nom , temp = 25c, v dd - v ss = 5.0v graph 3: active energy, pf = 1, vmains = v nom , temp = 25c, v dd - v ss = 5.0v graph 2: active energy, pf = 1, freq = 50hz, temp = 25c, v dd - v ss = 5.0v graph 4: active energy, pf = 1, freq = 50hz, vmains = v nom , temp = 25c sa9904b r6 r4 r1 0.2a to 100a 50hz ac phase 1 220v 50hz ac phase 1 iin1 iip1 vref vss vss cs sck vdd vdd r10 + - + - gnd gnd vdd vss gnd r1: 1.2 ? r2: 1.2 ? r3: 1.5k ? r4: 1.5k ? r5: 1.5k ? r6: 1.5k ? r7: 250k ? r8: 1k ? r9: 100k ? r10: 47k ? ct1 : tz76v (2500:1) p1: 1k ? c1: 22nf c2: 22nf c3: 5.6nf c4: 220nf c5: 220nf c6: 1 f x1: 3.5795mhz ct1 do 2.5v dc 2.5v dc vdd vss c4 c5 c6 phase angle between voltage and current 0 to 360 gnd ivp1 n n three phase source di osc2 osc1 agnd r3 r5 c2 c1 r2 iin2 iip2 same as iip1 / iin1 input network 0.2a to 100a 50hz ac phase 2 iin3 iip3 same as iip1 / iin1 input network 0.2a to 100a 50hz ac phase 3 r9 c3 gnd gnd r7 r8 p1 220v 50hz ac phase 2 n 220v 50hz ac phase 3 n same as ivp1 input network ivp2 same as ivp1 input network ivp3 x1 f50 spi interface to controller -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.1 1 10 100 %error %i max pf = 1 pf = 0.5 lag pf = 0.5 lead pf = -1 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.1 1 10 100 %error %i max freq = 50hz freq = 45hz freq = 65hz -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.1 1 10 100 %error %i max vmains = 100%vnom vmains = 50% vnom vmains = 115% vnom -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.1 1 10 100 %error %i max vdd-vss = 5.0v vdd-vss = 4.5v vdd-vss = 5.5v
spec - 0447 (rev. 7) 7 / 18 2 9 - 09 - 2017 sa9904b graph 5: reactive energy, freq = 50hz, vmains = v nom , temp = 25c, v dd - v ss = 5.0v graph 7: reactive energy, pf = 0 lag, vmains = v nom , temp = 25c, v dd - v ss = 5.0v graph 6: reactive energy, pf = 0 lag, freq = 50hz, temp = 25c, v dd - v ss = 5.0v graph 8: reactive energy, pf = 0 lag, freq = 50hz, vmains = v nom , temp = 25c -2.0 -1.5 -1.0 -0.5 0.0 0.5 0.1 1 10 100 %error %i max pf = 0 lag pf = 0.87 lag pf = -0.87 lag pf = 0 lead -1.5 -1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.1 1 10 100 %error %i max freq = 50hz freq = 45hz freq = 65hz -1.5 -1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.1 1 10 100 %error %i max vmains = 100%vnom vmains = 50% vnom vmains = 115% vnom -1.5 -1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.1 1 10 100 %error %i max vdd-vss = 5.0v vdd-vss = 4.5v vdd-vss = 5.5v
spec - 0447 (rev. 7) 8 / 18 2 9 - 09 - 2017 sa9904b functional description the sa9904b is a cmos mixed signal integrated circuit, which performs the measurement of active power, reactive power, rms voltage and mains frequency. the integrated circuit includes all the required functions for three phase power and energy measurement such as oversampl ing a/d converters for the voltage and current sense inputs, power calculation and energy integration. the sa9904b integrates instantaneous active and reactive power into 24 bit registers. rms voltage and frequency are continuously measured and stored in the respective registers. the mains voltage zero crossover is available on the f50 output. the spi interface of the sa9904b has a tri - state output that allows connection of more than one metering device on a single spi bus. figure 5 : typical architecture of an energy meter using the sa9904b in the typi cal meter architecture, a micro controller is used in conjunction with the sa9904b. in addition to communicating with the sa9904b the controller is used to read/write pa rameters to the eeprom, output pulses for fast calibration and to display the consumed active and reactive power, v rms and mains frequency information. other parameters such as i rms , phase angle etc. can be accurately calculated. theory of operation the sa 9904b includes all the required functions for three channel multifunction power and energy measurement. three pairs of identical ad converters sample the three phase voltage and current input signals. the three pairs of digital signals, accurately repres enting the voltage and current inputs, are used to calculate active energy, reactive energy, v rms and the mains frequency. these quantities are stored in 24 bit registers that can be accessed via the spi bus. the energy registers accumulate instantaneous e nergy . for given voltage and current signals the instantaneous active power is calculated by: ? ( ? ) = ? ( ? ) ? ( ? ) ? ( ? ) = ? ? cos ( ?? + ? ) ? ? cos ( ?? + ? ) let ? = ? ? ? , and ? ??? = ? ? 2 and ? ??? = ? ? 2 then ? ( ? ) = ? ? cos ( ?? + ? ) ? ? cos ( ?? + ? ? ? ) ? ( ? ) = ? ??? ? ??? ( cos ? + cos ( 2 ( ?? + ? ) ? ? ) ) where p(t) is the instantaneous power, v(t) is the instantaneous voltage signal, i(t) is the instantaneous current signal, v m is the amplitude of the voltage signal, i m is the amplitude of the current signal, ? is the phase angle of the voltage signal and ? is the phase angle of the current signal. the instantaneous power is integrated in the active energy registers. over time this removes the double mains frequency component cos(2( ? t+ ? ) - ? ) to provide the avera ge power information ? = 1 ? ? ( ? ) ?? ? 0 ? = ? ??? ? ??? cos ? where p is the average power and cos ? is the power factor. reactive power is calculated by applying a 90 degree phase shift to the voltage signal before multiplication: ? ( ? ) = ? ( ? ? ? 4 ? ) ? ( ? ) ? ( ? ) = ? ? cos ( ?? + ? ? ? 2 ? ) ? ? cos ( ?? + ? ) ? ( ? ) = ? ? sin ( ?? + ? ) ? ? cos ( ?? + ? ? ? ) ? ( ? ) = ? ??? ? ??? ( sin ? + sin ( 2 ( ?? + ? ) ? ? ) ) the instantaneous reactive power is integrated in the reactive energy registers. over time this removes the double mains frequency component sin(2( ? t+ ? ) - ? ) to provide the average reactive power information ? = 1 ? ? ( ? ) ?? ? 0 ? = ? ??? ? ??? sin ? where q is the average reactive power. n l1 l2 l3 powe r supply voltage sensing current sensing sa9904b active energy reactive energy v rms and frequency measurements microcontroller eeprom lcd leds spi
spec - 0447 (rev. 7) 9 / 18 2 9 - 09 - 2017 sa9904b linearity the sa 9904b is a cmos integrated circuit, which performs power/energy calculations across a dynamic range of 500:1 to an accuracy that exceeds the iec62053. a nalog inputs the input circuitry of the current and voltage sensor inputs is illustrated in figure 6 . these inputs are protected against electrostatic discharge through clamping diodes. the feedback loops from the outputs of the amplifiers a i and a v generate virtual short circuits between iip and iin as well as ivp and agnd. the current sens e inputs (iip and iin) are identical and balanced. the ad converters convert the signals on the voltage and current sense inputs to a digital format for further processing. all internal offsets are eliminated through the use of various cancellation techniq ues. figure 6 : analog input configuration power - on reset the sa9904b has a power - on reset circuitry that activates whenever the voltage between v dd and v ss is less than 3.6v 8%. power consumption the power consumption of the sa 9904b integ rated circuit is less than 50mw. input signals voltage reference (vref) a bias resistor of 47k ? sets optimum bias an d reference conditions on chip. current sense inputs (iip1/iin1, iip2/iin2, iip3/iin3) figure 7 shows the typical connections for the current sensor input for one channel. the circuit has to be repeated for the other two channels. at maximum rated mains current (i max ) the resistor values should be selected for input currents of 16a rms . the current sense inputs saturate at an input current of 17.6a rms (25a peak ), so this allows about 10% headroom until saturation occurs. the resistors ra and rb form the current transformers termination resistor. the reference level is connected in the centre of th e termination resistor to achieve purely differential input currents. the voltage drop across the termination resistors at maximum rated mains current (i max ) should be in the order of 100mv rms . the termination resistance should also be significantly smalle r than the dc resistance of the current transformers secondary winding. the resistors r1 to r4 define the current flowing into the device. for best performance the sa 9904b requires anti - alias filters on the current sense inputs. these filters are realized by means of the capacitors c1 and c2. the typical cut - off frequency of these filters should be between 10khz and 20khz. the optimum input network is achieved by setting th e input resistors equal, i.e. setting r1 = r2 = r3 = r4 = r c . this sets the equivalent resistance associated with each capacitor to r c /2. figure 7 : current sense input configuration a i iin iip vdd vss vdd vss a v ivp vdd vss agnd voltage sensor input current sensor input current channel adc voltage channel adc r3 r1 ra iin iip gnd ct1 current in i max 16 a rms r4 r2 rb current out gnd gnd c1 c2
spec - 0447 (rev. 7) 10 / 18 2 9 - 09 - 2017 sa9904b voltage sense inputs (ivp1, ivp2, ivp3) figure 8 shows the voltage sense input configuration for one channel. the circuit is identical for the other two channels. the voltage sense input saturates at an input current of 17.6a rms (25a peak ). the current into the voltage se nse input should therefore be set to 1 4 a rms at nominal mains voltage (v nom ) to allow for a mains voltage variation of up to + 15 % and C 50% without saturating the voltage sense input. for best performance the sa 9904b also requires an anti - alias filter on the voltage sense inputs. referring to figure 8 , the capacitor c1 is used to both implement the anti - alias filter as well as compensating for any phase shift caused by the current transformer. the resistor r4 defines the input current into the device. the optimum input network is achieved by setting r4 in the order of 100k ? . if r4 is made too large the capacitor c1 will be very small and the accuracy of the phase compensation could be affected by stray capacitances. figure 8 : voltage sense input configuration serial clock (sck) the sck pin is used to synchronize data interchange between the microcontroller and the sa9904b. the clock signal on this pin is generated by the microcontroller and determines the data transfer rate of the do and di pins. serial data in (di) the di pin is the serial data input pin for the sa9904b. data will be input at a rate determined by the serial clock (sck). d ata will be strobed by the sa9904b on the rising edge of sck only du ring an active chip select (cs). chip select (cs) the cs input is used to address the sa9904b. a high level on this pin enables the sa9904b to initiate data exchange. output signals serial data out (do) the do pin is the serial data output pin for the sa9904b. the serial clock (sck) determines the data output rate. data is only transferred out on the rising edge of sck during active chip select (cs). this output is tri - state when cs is inactive (low). it is recommended to use an external pull - up or pull - down resistor on do to ensure its state is always valid. mains voltage z ero c rossover (f50) the f50 output generates a signal, which follows the mains voltage zero crossings as shown in figure 9 . this output generates a pulse on the rising edge of the mains voltage zero crossing point. the pulse width is between 1ms and 2ms. internal logic ensures that this signal is generated from a valid phase. should all three phase s be missing but power still applied to the sa9904b this output will generate a cons t ant 54hz signal. the microcontroller can use this signal to extract the mains timing or synchronize to the mains voltage. figure 9 : mains voltage zero crossover spi interface description a serial peripheral interface bus (spi) is a synchronous bus used for data transfers between a microcontroller and the sa9904b. the pins do (serial data out), di (serial data in), cs (chip select), and sck (serial clock ) are used in the bus implementation. the sa9904b is the slave device with the microcontroller being the bus master. the cs input initiates and terminates data transfers. a sck signal (generated by the microcontroller) strobes data between the micro control ler and the sa9904b. the di and do pins are the serial data input and output pins for the sa9904b respectively. r4 r3 ivp gnd c1 r2 r1 gnd v nom 14 a rms voltage in neutral gnd r5 r5 << r4 << (r1 + r2 + r3) t phase voltage 1ms C 2ms f50
spec - 0447 (rev. 7) 11 / 18 2 9 - 09 - 2017 sa9904b register access table 1 lists the various register addresses. the sa9904b contains nine 24 bit registers representing t he active energy, reactive energy and the mains voltage for each phase. a tenth 24 bit register represents the mains frequency for any valid phase. the frequency register has been mapped to three addresses any of the three can be used to access it . table 1 : register addressing id register header bits address bits 5 4 3 2 1 0 1 active energy, channel 1 1 1 0 x x 0 0 0 0 2 reactive energy, channel 1 1 1 0 x x 0 0 0 1 3 voltage, channel 1 1 1 0 x x 0 0 1 0 4 frequency 1 1 0 x x 0 0 1 1 5 active energy, channel 2 1 1 0 x x 0 1 0 0 6 reactive energy, channel 2 1 1 0 x x 0 1 0 1 7 voltage, channel 2 1 1 0 x x 0 1 1 0 8 frequency 1 1 0 x x 0 1 1 1 9 active energy, channel 3 1 1 0 x x 1 0 0 0 10 reactive energy, channel 3 1 1 0 x x 1 0 0 1 11 voltage, channel 3 1 1 0 x x 1 0 1 0 12 frequency 1 1 0 x x 1 0 1 1 the header bit s 110 (0x06) form the read command must precede the 6 bit address of the register being accessed. when cs is high , data on the di pin is clocked into the sa9904b on the rising edge of sck. figure 11 shows the data clocked into di comprising of : 1 1 0 a5 a4 a3 a2 a1 a0 address locations a5 and a4 are included for compatibility with future developments. their state is ignored at present but it is best to set them to zero. the 9 bits needed for register addressing can be padded with leading zeros when the micro controller requires a n 8 bit spi word length. the following sequence is valid: 0 0 0 0 0 0 0 1 1 0 a5 a4 a3 a2 a1 a0 registers may be read individually and in any order. after a register has been read, the contents of the next register will be shifted out on the do pin with every sck clock cycle. this allows multiple subsequent registers to be read. data output on do will continue until cs is inactive. the do pin is tri - state when cs is inactive, allowing multiple spi devices to be connected to the bus. the content of each register consists of 24 bits of data. the most significant bit i s shifted out first. data format figure 11 shows the spi waveforms and figure 10 and table 2 the timing information. after the least significant digit of the address has been entered on the rising edge of sck, the ou tput do goes low. each subsequent rising edge transition on the sck pin will validate the next data bit on the do pin. for best reliability of the spi interface it is recommended to change cs and di together with the falling edge of sck and strobe do on th e falling edge of sck as well, as shown in figure 11 . figure 10 : spi waveform timing diagram table 2 : spi timing information parameter description min max t 1 sck rising edge to do valid 625ns 1.16s t 2 setup time for di and cs before rising edge of sck 20ns t 3 sck minimum high time 625ns t 4 sck minimum low time 625ns t 5 hold time for di and cs after rising edge of sck 625ns figure 11 : spi waveforms do di t 2 sck cs t 1 t 5 t 3 t 4 cs sck di do 1 1 0 a5 a4 a3 a2 a1 a0 d23 d22 d21 d0 d23 d22 d1 d0 d1 register data next register high impedance read command register address 0
spec - 0447 (rev. 7) 12 / 18 2 9 - 09 - 2017 sa9904b register description active and reactive registers the active and reactive energy measured on each channel of the sa9904b is accumulated in 6 distinct registers . each channel has its own active and reactive energy register . these registers are 24 bit up/down counters, that increment or decrement at a rate of 320 000 counts per second at rated conditions (nominal mains voltage v nom and maximum rated mains current i max ). the register values will increment for positive energy flow and decrement for negative energy flow. the active and reactive registers are not reset after access, so in order to determine the correct register value the previous value read must be subtracted from the c urrent reading. the data read from the registers represents the active or reactive power integrated over time. the increase or decrease between readings represent s the measured energy consumption since the previous register access. at rated conditions, the active and reactive registers will wrap aro und every 52 seconds. the micro controller software needs to take this condition into account when calculating the diffe rence between register values. the register difference is always computed correctly if 24 bit arithmetic is used, regardless if a wrap - around has occurred or not. if the controller software uses 32 bit arithmetic , the 24 bit register readings s hould be sig n extended to 32 bits. this ensures that the difference is computed correctly even if a register wrap - around has occurred. the active and reactive energy measured per register count can be calculated by applying the following formula: ?????? ??? ????? = ? ??? ? ??? 320000 where v nom is the n ominal r ated mains voltage of meter and i max is the m aximum rated mains current of meter . the result is watt seconds or var seconds. the active and reactive power measured on one channel by the sa9904b is calculated as follows: ????? = ? ??? ? ??? ? 320000 ? ??? where n is the d ifference in register values between successive register reads and t int is the t ime difference between successive register reads . voltage registers the three voltage registers contain the rms voltage measured on each channel of the device . this measurement is a true rms measurement which is accurate to 1% for a range of 50% to 115% of the rated mains voltage. the rms mains voltage me asured by the sa9904b is calculated as follows : ??? ????? ??????? = ? ??? ???? 700 where vreg is the voltage register value . the value of the voltage register will default to zero when the rms measurement produces a register value of less than 64. this occurs at a mains voltage of just below 10% v nom . the settling time of the rms measurement algorithm is in the order of 200 mains cycles. frequency register the single frequency register contains the measured mains frequency informatio n for a valid phase. internal logic ensures that the frequency information is generated from the same phase being used for the f50 output. only bits d0 to d9 are used for the mains frequency calculation result, however the remaining bits must still be cloc ked out as additional information can be derived from these data bits as indicated in table 3 . table 3 : frequency register bits allocation bits description d9d0 these bits represent a value that is used in the frequency calculation d17d10 unused , default value is zero d20, d19, d18 missing phase. these bits indicate which phase is missing during a lost phase condition. d 20 d19 d 18 status x x 1 phase 1 is missing x 1 x phase 2 is missing 1 x x phase 3 is missing d22, d21 the phase error status can be ascertained from these two bits. d2 2 d2 1 status 0 0 no phase error 1 0 phase sequence error x 1 missing phase d23 voltage zero crossover bit . this bit changes state with each rising edge of the mains voltage.
spec - 0447 (rev. 7) 13 / 18 2 9 - 09 - 2017 sa9904b the mains frequency measured by the sa9904b is calculated as follows: ????? ????????? = ? ??????? ???? 256 where f reg is the frequency register value in bits d9 to d0 and f crystal is the frequency of the external crystal . oscillator the sa9904b contains a crystal oscillator driver circuit requiring only an external crystal to be connected between osc1 and osc2. all other components are integrated on the device. the recommended crystal is a tv colour burst crystal (3.5795mhz). typical application the following description outlines the basic process required to design a typical three phase energy meter using the sa 9904b . the meter is a 3 - phase 4 - wire meter capable of measuring 3x220v/60a/50 hz with a precision better than class 1 on active energy and class 2 on reactive energy . the most important external circuits required for the sa 9904b are the current input networks, the voltage input networks as well as the bias resistor. all resistors should be 1% metal film resistors of the same type to minimize temperature effects. calibration of a micro controller based meter is typically done in software so the external circuits do not require calibration mechanisms. bias resistor a bias resistor of r34 = 47k ? sets optimum bias and reference currents on chip. current input networks three current transformers are used to measure the three line currents. the output of each current transformer is terminated with a low impedance resistor split into two equal parts to obtain purely differential current input signals. the voltage across the termination resistors is converted to the required differential input currents through the current input resistors. anti - alias filters are incorporated on these input resistors to filter any high frequency signal components that could affect the performance of the sa 9904b . the voltage drop across the current transformer termination resistors at maximum rated current should be in the order of 100mv rms . the current trans formers have a low phase shift and a turns ratio of 1:2500. the value of the termination resistors r1, r2 is therefore ? 1 = ? 2 = 100 ?? ? ?? ? ??? 1 2 2 = ? ? where n ct is the current transformer ratio (2500) and i max is the maximum input current (60a). the four current input resistors (r3, r4, r5, r6) should be of equal size to optimize the input networks low pass filtering characteristics, so the values can be calculated as follows: ? 3 = ? 4 = ? 5 = ? 6 = ? ??? ? ?? ? ? 2 16 ?? = 1 . 5 ? = ? ? for optimum performance the cut - off frequency of the anti - alias filter should be between 10khz and 20khz. the equivalent resistance associated with each capacitor is r c /2 so the capacitor values should be in the order of ? 1 = ? 2 = 1 ?? ?? ? ? = 1 ? 10 ??? 1 . 5 ? 22 ?? = ? ? where f ci is the cut - off frequency of the anti - alias filter of the current input network. the current input networks for channel 2 and channel 3 are identical. voltage input networks the voltage sense inputs require an input current of 1 4 a rms at v nom . the mains voltage is divided by means of a voltage divider to a lower voltage that is converted to the required input current by means of the input resistor. once again an anti - alias filter is required to remove any high frequency signals that could affe ct the performance of the sa9904b . the phase shift of the current transformers is compensated by means of this anti - alias filter as well, by purposefully increasing the cut - off frequency. the input resistor r22 sets the current input into the device. this resistor should not be too large else the capacitor for the anti - alias filter will be quite small which could cause inaccurate phase shift due to parasitic capacitances. therefore r22 = 100k ? is chosen . r23 should be significantly smaller than r22, but no t too small in order to limit the power dissipation of the voltage input network. hence r23 = 4 . 3 k ?? is chosen. now let r a = r19 + r20 + r21 and ? ? = ? 23 ( 220 ? 1 . 4 ? ? 1 ) 671 ? so choose r19 = r20 = r21 = 2 2 0k ? .
spec - 0447 (rev. 7) 14 / 18 2 9 - 09 - 2017 sa9904b the cut - off frequency of the anti - alias filt er is adjusted so that the phase shift of the voltage input network is identical to the sum of the phase shifts of the current transformer and the current input network. the phase shift of the current input network is ? ?? = ? tan ? 1 ( ? ? ? ? ? 50 ?? ) ? 0 . 297 the phase shift required on the voltage input network is therefore ? ?? = ? ?? ? ? ?? = ? 0 . 297 + 0 . 09 = ? 0 . 207 where ? ct is the phase shift of the current transformer which is typically about 0.09 degrees for a good quality current transformer. neglecting r19, r20, r21 and r22 because all these resistors are significantly larger than r23 the capacitance required to achieve the - 0.207 degree phase shift is ? 7 = | tan ? ?? | 2 ? ? 23 50 ?? 2 . 7 ?? resulting in a cut - off frequency of ? ?? = 1 2 ? ? 23 ? 7 = 13 . 7 ??? the value of the cut - off frequency of the voltage input network is less critical than that of the current input network because the dynamic range of the voltage input is small. a cut - off frequency between 10khz and 25khz is acceptable. the voltage input networks for channel 2 and channel 3 are identical figure 12 : typical application circuit 6 14 15 vdd vss vref iip1 iin1 sa9904b u1 osc1 do di sck cs f50 ivp3 ivp2 ivp1 agnd 16 17 20 3 7 13 8 12 9 10 osc2 11 18 19 ct1 r2 2 ? c2 r1 2 ? r5 r6 r3 r4 1.5k ? 1.5k ? 1.5k ? 1.5k ? c1 22nf 22nf 1 2 ct2 r8 2 ? c4 r7 2 ? r11 r12 r9 r10 1.5k ? 1.5k ? 1.5k ? 1.5k ? c3 22nf 22nf 4 5 ct3 r14 2 ? c6 r13 2 ? r17 r18 r15 r16 1.5k ? 1.5k ? 1.5k ? 1.5k ? c5 22nf 22nf iip2 iin3 r34 47k ? - 2.5v +2.5v r24 240k ? r29 220k ? r19 220k ? r25 220k ? r30 220k ? r20 220k ? r26 220k ? r31 220k ? r21 220k ? r27 100k ? r32 100k ? r22 100k ? r28 4.3k ? r33 4.3k ? r23 4.3k ? 0v 0v iin2 live 1 in live 2 in live 3 in neutral 0v iip3 live 3 out live 2 out live 1 out c7 2.7nf c8 2.7nf 2.7nf c9 0v c10 220nf c11 220nf c12 1 f +2.5v - 2.5v 0v 0v 0v 0v cs sck di f50 do x1 3.5795mhz
spec - 0447 (rev. 7) 15 / 18 2 9 - 09 - 2017 sa9904b table 4 : component list for typical application symbol description u1 energy metering device, sa 9904bsa r r1, r2 resistor, 2 ? , 1%, metal film r3, r4 1 , r5, r6 1 resistor, 1.5k ? , 1%, metal film r7, r8 resistor, 2 ? , 1%, metal film r9, r10 1 , r11, r12 1 resistor, 1.5k ? , 1%, metal film r13, r14 resistor, 2 ? , 1%, metal film r15, r16 1 , r17, r18 1 resistor, 1.5k ? , 1%, metal film r19, r24, r29 resistor, 2 2 0k ? , 1%, metal film r20, r25, r30 resistor, 220k ? , 1%, metal film r21, r26, r31 resistor, 22 0k ? , 1%, metal film r22 1 , r27 1 , r32 1 resistor, 100k ? , 1%, metal film r23, r28, r33 resistor, 4 . 3 k ? , 1%, metal film r34 1 resistor, 47k ? , 1%, metal film c1, c2 capacitor, 22nf, ceramic c3, c4 capacitor, 22nf, ceramic c5, c6 capacitor, 22nf, ceramic c7, c8, c9 capacitor, 2 . 7 nf, ceramic c10 2 , c11 2 capacitor, 220nf, ceramic c12 2 capacitor, 1f, ceramic x1 crystal , 3.5795mhz note 1: resistors r4, r6, r10, r12, r16, r18, r22, r27, r32 and r34 must be positioned as close as possible to the respective device pins note 2: capacitors c10, c11 and c12 must be positioned as close as possible to the v dd and v ss power supply pins
spec - 0447 (rev. 7) 16 / 18 2 9 - 09 - 2017 sa9904b package dimensions soic2 0 package dimensions are shown in inches
spec - 0447 (rev. 7) 17 / 18 2 9 - 09 - 2017 sa9904b notes
spec - 0447 (rev. 7) 18 / 18 2 9 - 09 - 2017 sa9904b d isclaimer the information contained in this document is confidential and proprietary to integrated circuit design centre (pty) ltd ("ic dc"), a d ivision of south african micro - e lectronic systems (pty) ltd ("sames"), and may not be copied or disclosed to a t hird party, in whole or in part, without the express written consent of icdc. the information contained herein is current as of the date of publication; however, delivery of this document shall not under any circumstances create any implication that the in formation contained herein is correct as of any time subsequent to such date. icdc does not undertake to inform any recipient of this document of any changes in the information contained herein, and icdc expressly reserves the right to make changes in such information, without notification, even if such changes would render information contained herein inaccurate or incomplete. i cdc makes no representation or warranty that any circuit designed by reference to the information contained herein, will function without errors and as intended by the designer . any sales or technical questions may be sent to our support e - mail address: support@sames.co.za for the latest updates on datasheets, please visit our web site: http://www.sames.co.za. integrated circuit design centre (pty) ltd a division of south african micro - electronic systems (pty) ltd tel: 012 333 6021 tel int: 00 27 12 333 6021 fax: 012 333 6393 fax int: 00 27 12 333 6393 po box 15888 lynn east 0039 repu blic of south africa unit 4, persequor close 49 de havilland crescent persequor technopark lynnwood, pretoria republic of south africa

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